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cy7c1161v18, cy7c1176v18 cy7c1163v18, cy7c1165v18 18-mbit qdr?-ii+ sram 4-word burst architecture (2.5 cycle read latency) cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-06582 rev. *d revised march 06, 2008 features separate independent read and write data ports ? supports concurrent transactions 300 mhz to 400 mhz clock for high bandwidth 4-word burst to reduce address bus frequency double data rate (ddr) interfaces on both read and write ports (data transferred at 800 mhz) at 400 mhz read latency of 2.5 clock cycles two input clocks (k and k ) for precise ddr timing ? sram uses rising edges only echo clocks (cq and cq ) simplify data capture in high speed systems single multiplexed address input bus latches address inputs for both read and write ports separate port selects for depth expansion data valid pin (qvld) to indicate valid data on the output synchronous internally self-timed writes available in x8, x9, x18, and x36 configurations full data coherency providing most current data core v dd = 1.8v 0.1v; io v ddq = 1.4v to v dd [1] available in 165-ball fbga package (13 x 15 x 1.4 mm) offered in both pb-free and non pb-free packages variable drive hstl output buffers jtag 1149.1 compatible test access port delay lock loop (dll) for accurate data placement configurations with cycle read latency of 2.5 cycles: cy7c1161v18 ? 2m x 8 cy7c1176v18 ? 2m x 9 cy7c1163v18 ? 1m x 18 cy7c1165v18 ? 512k x 36 functional description the cy7c1161v18, cy7c11 76v18, cy7c1163v18, and cy7c1165v18 are 1.8v synchronous pipelined srams equipped with qdr?-ii+ architecture. qdr-ii+ architecture consists of two separate ports to access the memory array. the read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. qdr-ii+ architectu re has separate data inputs and data outputs to completely eliminate the need to turn around the data bus that is required with co mmon io devices. each port can be accessed through a common address bus. addresses for read and write addresses are latched onto alternate rising edges of the input (k) clock. accesses to the qdr-ii+ read and write ports are completely independent of one another. in order to maximize data throughput, both read and write ports are equipped with double data rate (ddr) interfaces. each address location is associated with four 8-bit words (cy7c1161v18), 9-bit words (cy7c1176v18), 18-bit words (cy7c1163v18), or 36-bit words (cy7c1165v18) that burst sequentially into or out of the device. because data can be trans- ferred into and out of the device on every rising edge of both input clocks k and k , memory bandwidth is maximized while simpli- fying system design by el iminating bus turnarounds. depth expansion is accomplished with port selects for each port. port selects allow each port to operate independently. all synchronous inputs pass through input registers controlled by the k or k input clocks. all data outputs pass through output registers controlled by the or k or k input clocks. writes are conducted with on-chip synchron ous self-timed write circuitry. selection guide description 400 mhz 375 mhz 333 mhz 300 mhz unit maximum operating frequency 400 375 333 300 mhz maximum operating current 1080 1020 920 850 ma note 1. the qdr consortium specification for v ddq is 1.5v + 0.1v. the cypress qdr devices exceed the qdr consor tium specification and are capable of supporting v ddq = 1.4v to v dd . [+] feedback [+] feedback
cy7c1161v18, cy7c1176v18 cy7c1163v18, cy7c1165v18 document number: 001-06582 rev. *d page 2 of 29 logic block diagram (cy7c1161v18) logic block diagram (cy7c1176v18) 512k x 8 array clk a (18:0) gen. k k control logic address register d [7:0] read add. decode read data reg. rps wps q [7:0] control logic address register reg. reg. reg. 16 19 8 32 8 nws [1:0] v ref write add. decode write reg 16 a (18:0) 19 512k x 8 array 512k x 8 array 512k x 8 array write reg write reg write reg 8 cq cq doff qvld 512k x 9 array clk a (18:0) gen. k k control logic address register d [8:0] read add. decode read data reg. rps wps q [8:0] control logic address register reg. reg. reg. 18 19 9 36 9 bws [0] v ref write add. decode write reg 18 a (18:0) 19 512k x 9 array 512k x 9 array 512k x 9 array write reg write reg write reg 9 cq cq doff qvld [+] feedback [+] feedback
cy7c1161v18, cy7c1176v18 cy7c1163v18, cy7c1165v18 document number: 001-06582 rev. *d page 3 of 29 logic block diagram (cy7c1163v18) logic block diagram (cy7c1165v18) 256k x 18 array clk a (17:0) gen. k k control logic address register d [17:0] read add. decode read data reg. rps wps q [17:0] control logic address register reg. reg. reg. 36 18 18 72 18 bws [1:0] v ref write add. decode write reg 36 a (17:0) 18 256k x 18 array 256k x 18 array 256k x 18 array write reg write reg write reg 18 cq cq doff qvld 128k x 36 array clk a (16:0) gen. k k control logic address register d [35:0] read add. decode read data reg. rps wps q [35:0] control logic address register reg. reg. reg. 72 17 36 144 36 bws [3:0] v ref write add. decode write reg 72 a (16:0) 17 128k x 36 array 128k x 36 array 128k x 36 array write reg write reg write reg 36 cq cq doff qvld [+] feedback [+] feedback
cy7c1161v18, cy7c1176v18 cy7c1163v18, cy7c1165v18 document number: 001-06582 rev. *d page 4 of 29 pin configurations cy7c1161v18 (2m x 8) 165-ball fbga (13 x 15 x 1.4 mm) pinout 23 4 5 6 7 1 a b c d e f g h j k l m n p r a cq nc nc nc nc doff nc nc/72m a nws 1 k wps nc/144m nc nc nc nc nc tdo nc nc d5 nc nc nc tck nc nc a nc/288m k nws 0 v ss anca nc v ss v ss v ss v ss v dd a v ss v ss v ss v dd q4 nc v ddq nc nc nc nc q7 a v ddq v ss v ddq v dd v dd q5 v ddq v dd v ddq v dd v ddq v dd v ss v dd v ddq v ddq v ss v ss v ss v ss a a nc v ss a a a d4 v ss nc v ss nc nc v ref v ss v dd v ss v ss a v ss qvld nc q6 nc d7 d6 v dd a 8 91011 nc anc/36m rps cq a nc nc q3 v ss nc nc d3 nc v ss nc q2 nc nc nc v ref nc nc v ddq nc v ddq nc nc v ddq v ddq v ddq d1 v ddq nc q1 nc v ddq v ddq nc v ss nc d0 nc tdi tms v ss a nc a nc d2 nc zq nc q0 nc nc nc nc a nc/144m cy7c1176v18 (2m x 9) 23 4 5 6 7 1 a b c d e f g h j k l m n p r a cq nc nc nc nc doff nc nc/72m a nc k wps nc/144m nc nc nc nc nc tdo nc nc d6 nc nc nc tck nc nc a nc/288m k bws 0 v ss anca nc v ss v ss v ss v ss v dd a v ss v ss v ss v dd q5 nc v ddq nc nc nc nc q8 a v ddq v ss v ddq v dd v dd q6 v ddq v dd v ddq v dd v ddq v dd v ss v dd v ddq v ddq v ss v ss v ss v ss a a nc v ss a a a d5 v ss nc v ss nc nc v ref v ss v dd v ss v ss a v ss qvld nc q7 nc d8 d7 v dd a 8 91011 q0 anc/36m rps cq a nc nc q4 v ss nc nc d4 nc v ss nc q3 nc nc nc v ref nc nc v ddq nc v ddq nc nc v ddq v ddq v ddq d2 v ddq nc q2 nc v ddq v ddq nc v ss nc d1 nc tdi tms v ss a nc a nc d3 nc zq nc q1 nc nc d0 nc a nc nc [+] feedback [+] feedback
cy7c1161v18, cy7c1176v18 cy7c1163v18, cy7c1165v18 document number: 001-06582 rev. *d page 5 of 29 pin configurations (continued) cy7c1163v18 (1m x 18) 165-ball fbga (13 x 15 x 1.4 mm) pinout 23 4 56 7 1 a b c d e f g h j k l m n p r a cq nc nc nc nc doff nc nc/144m nc/36m bws 1 k wps nc/288m q9 d9 nc nc nc tdo nc nc d13 nc nc nc tck nc d10 a nc k bws 0 v ss anca q10 v ss v ss v ss v ss v dd a v ss v ss v ss v dd q11 d12 v ddq d14 q14 d16 q16 q17 a v ddq v ss v ddq v dd v dd q13 v ddq v dd v ddq v dd v ddq v dd v ss v dd v ddq v ddq v ss v ss v ss v ss a a v ss a a a d11 v ss nc v ss q12 nc v ref v ss v dd v ss v ss a v ss qvld nc q15 nc d17 d15 v dd a 8 91011 q0 anc/72m rps cq a nc nc q8 v ss nc q7 d8 nc v ss nc q6 d5 nc nc v ref nc q3 v ddq nc v ddq nc q5 v ddq v ddq v ddq d4 v ddq nc q4 nc v ddq v ddq nc v ss nc d2 nc tdi tms v ss a nc a d7 d6 nc zq d3 q2 d1 q1 d0 nc a nc cy7c1165v18 (512k x 36) 23 456 7 1 a b c d e f g h j k l m n p r a cq q27 d27 d28 d34 doff q33 nc/288m nc/72m bws 2 k wps bws 1 q18 d18 q30 d31 d33 tdo q28 d29 d22 d32 q34 q31 tck d35 d19 a bws 3 k bws 0 v ss anca q19 v ss v ss v ss v ss v dd a v ss v ss v ss v dd q20 d21 v ddq d23 q23 d25 q25 q26 a v ddq v ss v ddq v dd v dd q22 v ddq v dd v ddq v dd v ddq v dd v ss v dd v ddq v ddq v ss v ss v ss v ss a a nc v ss a a a d20 v ss q29 v ss q21 d30 v ref v ss v dd v ss v ss a v ss qvld q32 q24 q35 d26 d24 v dd a 891011 q0 nc/36m nc/144m rps cq a d17 q17 q8 v ss d16 q7 d8 q16 v ss d15 q6 d5 d9 q14 v ref q11 q3 v ddq q15 v ddq d14 q5 v ddq v ddq v ddq d4 v ddq d12 q4 q12 v ddq v ddq d11 v ss d10 d2 q10 tdi tms v ss a q9 a d7 d6 d13 zq d3 q2 d1 q1 d0 q13 a [+] feedback [+] feedback
cy7c1161v18, cy7c1176v18 cy7c1163v18, cy7c1165v18 document number: 001-06582 rev. *d page 6 of 29 pin definitions pin name io pin description d [x:0] input- synchronous data input signals . sampled on the rising edge of k and k clocks during valid write operations. cy7c1161v18 ? d [7:0] cy7c1176v18 ? d [8:0] cy7c1163v18 ? d [17:0] cy7c1165v18 ? d [35:0] wps input- synchronous write port select ? active low . sampled on the rising edge of the k clock. when asserted active, a write operation is initiated. deasserting deselects the write port. deselecting the write port causes d [x:0] to be ignored. nws 0 , nws 1 , input- synchronous nibble write select 0, 1 ? active low ( cy7c1161v18 only ). sampled on the rising edge of the k and k clocks during write operations. used to select the nibble that is wri tten into the device. nws 0 controls d [3:0] and nws 1 controls d [7:4] . all the nibble write selects are sampled on the sa me edge as the data. deselecting a nibble write select causes the corresponding nibble of data to be ignored and not written into the device. bws 0 , bws 1 , bws 2 , bws 3 input- synchronous byte write select 0, 1, 2, and 3 ? active low . sampled on the rising edge of the k and k clocks during write operations. used to select the byte that is written into the device during the current portion of the write operatio n. bytes not written remain unaltered. cy7c1176v18 ? bws 0 controls d [8:0]. cy7c1163v18 ? bws 0 controls d [8:0] and bws 1 controls d [17:9].. cy7c1165v18 ? bws 0 controls d [8:0] , bws 1 controls d [17:9] , bws 2 controls d [26:18], and bws 3 controls d [35:27]. all the byte write selects are sampled on the same edge as the data. deselect ing a byte write select causes the corresponding byte of data to be ignored and not written into the device. a input- synchronous address inputs . sampled on the rising edge of the k clock during active read and write operations. these address inputs are multiplexed for both read and write operations. internally, the device is organized as 2m x 8 (4 arrays each of 512k x 8) for cy7c1161v18, 2m x 9 (4 arrays each of 512k x 9) for cy7c1176v18, 1m x 18 (4 arrays each of 256k x 18) for cy7c1163v18, and 512k x 36 (4 arrays each of 128k x 36) for cy7c1165v18. ther efore, only 19 address inputs are needed to access the entire memory array of cy7c1161v18 and cy7c 1176v18, 18 address inputs for cy7c1163v18, and 17 address inputs for cy7c1165v18. these in puts are ignored when the appropriate port is deselected. q [x:0] outputs- synchronous data output signals . these pins drive out the requested data during a read operation. valid data is driven out on the risi ng edge of both the k and k clocks during read o perations or k and k when in single clock mode. when the read port is deselected, q [x:0] are automatically tri-stated. cy7c1161v18 ? q [7:0] . cy7c1176v18 ? q [8:0] . cy7c1163v18 ? q [17:0] . cy7c1165v18 ? q [35:0] . rps input- synchronous read port select ? active low . sampled on the rising edge of positive input clock (k). when active, a read operation is initiated. deasserting causes the read port to be desel ected. when deselected, the pending access is enabled to complete and the out put drivers are automatically tri-stated following the next rising edge of the k clock. each read acce ss consists of a burst of four sequential transfers. qvld valid output indicator valid output indicator . indicates valid output data. qvld is edge-aligned with cq and cq . k input- clock positive input clock input . rising edge of k is used to capture synchronous inputs to the device and to drive out data through q [x:0] when in single clock mode. all accesses are initiated on the rising edge of k. k input- clock negative input clock input . k is used to capture synchronous inputs presented to the device and to drive out data through q [x:0] when in single clock mode. cq echo clock synchronous echo clock outputs . this is a free running clock and is synchronized to the input clock (k) of the qdr-ii+. the timings for the echo clocks are shown in ?switching characteristics? on page 23 . [+] feedback [+] feedback
cy7c1161v18, cy7c1176v18 cy7c1163v18, cy7c1165v18 document number: 001-06582 rev. *d page 7 of 29 cq echo clock synchronous echo clock outputs . this is a free running clock and is synchronized to the input clock (k ) of the qdr-ii+. the timings fo r the echo clocks are shown in ?switching characteristics? on page 23. zq input output impedance matching input . used to tune the device out puts to the system data bus impedance. cq, cq and q [x:0] output impedance are set to 0.2 x rq, where rq is a resistor connected between zq and ground. alternativel y, this pin is connected directly to v ddq , which enables the minimum impedance mode. this pin canno t be connected directly to gnd or left uncon- nected. doff input dll turn off ? active low . connecting this pin to ground turns off the dll inside the device. the timings in the dll turned-off operation are different fr om those listed in this data sheet. for normal operation, this pin is connected to a pull up through a 10 k or less pull up resistor. the device behaves in qdr-i mode when the dl l is turned off. in this mode, t he device operates at a frequency of up to 167 mhz with qdr-i timing. tdo output tdo for jtag . tck input tck pin for jtag . tdi input tdi pin for jtag . tms input tms pin for jtag . nc n/a not connected to the die . can be tied to any voltage level. nc/36m n/a not connected to the die . can be tied to any voltage level. nc/72m n/a not connected to the die . can be tied to any voltage level. nc /144m n/a not connected to the die . can be tied to any voltage level. nc /288m n/a not connected to the die . can be tied to any voltage level. v ref input- reference reference voltage input . static input used to set the reference level for hstl inputs, outputs, and ac measurement points. v dd power supply power supply inputs to the core of the device . v ss ground ground for the device . v ddq power supply power supply inputs for the outputs of the device . pin definitions (continued) pin name io pin description [+] feedback [+] feedback
cy7c1161v18, cy7c1176v18 cy7c1163v18, cy7c1165v18 document number: 001-06582 rev. *d page 8 of 29 functional overview the cy7c1161v18, cy7c11 76v18, cy7c1163v18, and cy7c1165v18 are synchronous pipelined burst srams equipped with both a read port and a write port. the read port is dedicated to read operations and the write port is dedicated to write operations. data flows into the sram through the write port and out through the read port. these devices multiplex the address inputs in order to minimize the number of address pins required. by having separate re ad and write ports , the qdr-ii+ completely eliminates the need to ?turn-around? the data bus. it avoids any possible data content ion, thereby, simplifying system design. each access consists of four 8-bit data transfers in the case of cy7c1161v18, four 9-bit data transfers in the case of cy7c1176v18, four 18-bit data transfers in the case of cy7c1163v18, and four 36-bit da ta transfers in the case of cy7c1165v18 in two clock cycles. accesses for both ports are initiated on the positive input clock (k). all synchronous input and ou tput timings are referenced to the rising edge of the input clocks (k/k ). all synchronous data inputs (d [x:0] ) pass through input registers controlled by the input clocks (k and k ). all synchronous data outputs (q [x:0] ) pass through output registers controlled by the rising edge of the i nput clocks (k and k ) also. all synchronous control (rps , wps , bws [x:0] ) inputs pass through input registers controlled by the rising edge of the input clocks (k and k ). cy7c1163v18 is described in the following sections. the same basic descriptions apply to cy7c1161v18, cy7c1176v18, and cy7c1165v18. read operations the cy7c1163v18 is organized internally as four arrays of 256k x 18. accesses are completed in a burst of four sequential 18-bit data words. read operations ar e initiated by asserting rps active at the rising edge of the positive input clock (k). the address presented to address in puts are stored in the read address register. following the next two k clock rises, the corre- sponding lowest order 18-bit wo rd of data is driven onto the q [17:0] using k as the output timing reference. on the subse- quent rising edge of k, the next 18 -bit data word is driven onto the q [17:0] . this process continues until all four 18-bit data words have been driven out onto q [17:0] . the requested data is valid 0.45 ns from the rising edge of the input clock k or k . in order to maintain the internal logic, each read access must be allowed to complete. each read access consists of four 18-bit data words and takes two clock cycles to complete. therefore, read accesses to the device cannot be initiated on two consecutive k clock rises. the internal logic of the device ignores the second read request. read accesses can be initiated on every other k clock rise. doing so pipelines the data flow such that data is transferred out of the device on every rising edge of the input clocks k and k . when the read port is deselec ted, the cy7c1163v18 first completes the pending read transactions. synchronous internal circuitry automatically tri-states the outputs following the next rising edge of the negative input clock (k ). this allows for a seamless transition between devices without the insertion of wait states in a depth expanded memory. write operations write operations are initiated by asserting wps active at the rising edge of the positive input clock (k). on the following k clock rise, the data presented to d [17:0] is latched and stored into the lower 18-bit write data register, provided bws [1:0] are both asserted active. on the subsequent rising edge of the negative input clock (k ), the information presented to d [17:0] is also stored into the write data register, provided bws [1:0] are both asserted active. this process continues for one more cycle until four 18-bit words (a total of 72 bits) of data are stored in the sram. the 72 bits of data are then written into the memory array at the specified location. therefore, write accesses to the device cannot be initiated on two consecutive k clock rises. the internal logic of the device ignores the second write request. write accesses are initiated on every other rising edge of the positive input clock (k). doing so pipelines the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks (k and k ). when deselected, the write port ignores all inputs after the pending write operati ons are completed. byte write operations byte write operations are su pported by the cy7c1163v18. a write operation is initiated as described in the write operations section above. the bytes that are written are determined by bws 0 and bws 1 , which are sampled with each set of 18-bit data words. asserting the appropriate byte write select input during the data portion of a write enabl es the data being presented to be latched and written into the device. deasserting the byte write select input during the data porti on of a write allows the data stored in the device for that byte to remain unaltered. this feature is used to simplify read, modify, and write operations to a byte write operation. concurrent transactions the read and write ports on the cy7c1163v18 operate completely independent of one another. because each port latches the address inputs on different clock edges, the user can read or write to any location, regardless of the transaction on the other port. if the ports access the same location when a read follows a write in su ccessive clock cycles, the sram delivers the most recent information asso ciated with the specified address location. this includes forwarding data from a write cycle initiated on the previous k clock rise. read accesses and write access are scheduled such that one transaction is initia ted on any clock cycle. if both ports are selected on the same k clock rise, the arbitration depends on the previous state of the sram. if both ports are deselected, the read port takes priority. if a read is initiated on the previous cycle, the write port assumes priority (because read operations cannot be initiated on consecutive cycles). if a write was initiated on the previous cycle, the read port assumes priority (because write operations cannot be initiated on consecutive cycles). therefore, asserting both port selects active from a deselected state results in alternating read or write oper ations initiated, with the first access being a read. [+] feedback [+] feedback
cy7c1161v18, cy7c1176v18 cy7c1163v18, cy7c1165v18 document number: 001-06582 rev. *d page 9 of 29 depth expansion the cy7c1163v18 has a port select input for each port. this enables easy depth expansion. both port selects are only sampled on the rising edge of t he positive input clock (k). each port select input can deselect the specified port. deselecting a port does not affect the other port. all pending transactions (read and write) are completed before the device is deselected. programmable impedance an external resistor, rq, must be connected between the zq pin on the sram and v ss to enable the sram to adjust its output driver impedance. the value of rq must be 5x the value of the intended line impedance driven by the sram. the allowable range of rq to guarantee impedance matching with a tolerance of 15% is between 175 and 350 , with v ddq =1.5v. the output impedance is adjusted every 1024 cycles upon power up to account for drifts in supply voltage and temperature. echo clocks echo clocks are provided on the qd r-ii+ to simplify data capture on high speed systems. two ec ho clocks are generated by the qdr-ii+. cq is referenced with respect to k and cq is refer- enced with respect to k . these are free running clocks and are synchronized to the input clock of the qdr-ii+. the timings for the echo clocks are shown in the ac timing table. valid data indicator (qvld) qvld is provided on the qdr-ii+ to simplify data capture on high speed systems. the qvld is gen erated by the qdr-ii+ device along with data output. this signal is also edge-aligned with the echo clock and follows the timing of any data pin. this signal is asserted half a cycle before valid data arrives. dll these chips utilize a delay lock loop (dll) that is designed to function between 120 mhz and the specified maximum clock frequency. the dll may be disabled by applying ground to the doff pin. when the dll is turned off, the device behaves in qdr-i mode (with 1.0 cycle lat ency and a longer access time). for more information, refer to the application note, ? dll consid- erations in qdrii/ddrii/qdrii+/ddrii+ .? the dll can also be reset by slowing or stopping the input clocks k and k for a minimum of 30 ns. however, it is not necessary for the dll to be reset in order to lock to the desired frequency. during power up when the doff is tied high, the dll is locked after 2048 cycles of stable clock. [+] feedback [+] feedback
cy7c1161v18, cy7c1176v18 cy7c1163v18, cy7c1165v18 document number: 001-06582 rev. *d page 10 of 29 application example figure 1 shows four qdr-ii+ used in an application. figure 1. application example truth table the truth table for the cy7c1161v18, cy7c11 76v18, cy7c1163v18, and cy7c1165v18 follows. [3, 4, 5, 6, 7, 8] operation k rps wps dq dq dq dq write cycle : load address on rising edge of k; input write data on two consecutive k and k rising edges. l-h h [9] l [10] d(a) at k(t + 1) d(a + 1) at k (t + 1) d(a + 2) at k(t + 2) d(a + 3) at k (t + 2) read cycle (2.5 cycle latency): load address on rising edge of k; wait one and a half cycle; read data on two consecutive k and k rising edges. l-h l [10] x q(a) at k (t + 2) q(a + 1) at k(t + 3) q(a + 2) at k (t + 3) q(a + 3) at k(t + 4) nop : no operation. l-h h h d = x q = high z d = x q = high z d = x q = high z d = x q = high z standby : clock stopped. stopped x x previous state previous state previous state previous state bus master (cpu or asic) data in data out address source k source k vt vt vt r r clkin/clkin d a k sram #4 rq = 250 ohms zq cq/cq q k rps wps bws d a k sram #1 rq = 250 ohms zq cq/cq q k rps wps bws rps wps bws r = 50ohms, vt = v /2 ddq r notes 2. the above application shows four qdr-ii+ being used. 3. x = ?don't care,? h = logic high, l = logic low, represents rising edge. 4. device powers up deselected and the outputs in a tri-state condition. 5. ?a? represents address location latched by the devices when trans action was initiated. a + 1, a + 2, and a + 3 represents the address sequence in the burst. 6. ?t? represents the cycle at which a read or write operation is started. t + 1, t + 2, t + 3 and t + 4 are the first, second, third, and fourth clock cycles, respectively succeeding the ?t? clock cycle. 7. data inputs are registered at k and k rising edges. data outputs are delivered on k and k rising edges. 8. it is recommended that k = k = high when clock is stopped. this is not essential, but permits most rapid restart by overcoming transmission line charging s ymmetrically. 9. if this signal was low to initiate the previous cycl e, this signal becomes a ?don?t care? for this operation. 10. this signal was high on previous k clock rise. initiating c onsecutive read or write operations on consecutive k clock rises is not permitted. the device ignores the second read or write request. [+] feedback [+] feedback
cy7c1161v18, cy7c1176v18 cy7c1163v18, cy7c1165v18 document number: 001-06582 rev. *d page 11 of 29 write cycle descriptions the write cycle descriptions of cy 7c1161v18 and cy7c1163v18 follow. [3, 11] bws 0 / nws 0 bws 1 / nws 1 k k comments l l l?h ? during the data portion of a write sequence : cy7c1161v18 ? both nibbles (d [7:0] ) are written into the device. cy7c1163v18 ? both bytes (d [17:0] ) are written into the device. l l ? l-h during the data portion of a write sequence : cy7c1161v18 ? both nibbles (d [7:0] ) are written into the device. cy7c1163v18 ? both bytes (d [17:0] ) are written into the device. l h l?h ? during the data portion of a write sequence : cy7c1161v18 ? only the lower nibble (d [3:0] ) is written into the device, d [7:4] remains unaltered. cy7c1163v18 ? only the lower byte (d [8:0] ) is written into the device, d [17:9] remains unaltered. l h ? l?h during the data portion of a write sequence : cy7c1161v18 ? only the lower nibble (d [3:0] ) is written into the device, d [7:4] remains unaltered. cy7c1163v18 ? only the lower byte (d [8:0] ) is written into the device, d [17:9] remains unaltered. h l l?h ? during the data portion of a write sequence : cy7c1161v18 ? only the upper nibble (d [7:4] ) is written into the device, d [3:0] remains unaltered. cy7c1163v18 ? only the upper byte (d [17:9] ) is written into the device, d [8:0] remains unaltered. h l ? l?h during the data portion of a write sequence : cy7c1161v18 ? only the upper nibble (d [7:4] ) is written into the device, d [3:0] remains unaltered. cy7c1163v18 ? only the upper byte (d [17:9] ) is written into the device, d [8:0] remains unaltered. h h l?h ? no data is written into the device during this portion of a write operation. h h ? l?h no data is written into the device during this portion of a write operation. the write cycle ope ration of cy7c1176v18 follows. [3, 11] bws 0 k k comments l l?h ? during the data portion of a write sequence, the single byte (d [8:0] ) is written into the device. l ? l?h during the data portion of a write sequence, the single byte (d [8:0] ) is written into the device. h l?h ? no data is written into the device during this portion of a write operation. h ? l?h no data is written into the device during this portion of a write operation. note 11. is based upon a write cycle was initiated per the write cycle description truth table. nws 0 , nws 1 , bws 0 , bws 1 , bws 2 , and bws 3 can be altered on different portions of a write cycle, as long as the setup and hold requirements are achieved. [+] feedback [+] feedback
cy7c1161v18, cy7c1176v18 cy7c1163v18, cy7c1165v18 document number: 001-06582 rev. *d page 12 of 29 the write cycle descriptions of cy7c1165v18 follows. [3, 11] bws 0 bws 1 bws 2 bws 3 k k comments lllll?h?during the data portion of a write sequence, all four bytes (d [35:0] ) are written into the device. llll?l?hduring the data portion of a write sequence, all four bytes (d [35:0] ) are written into the device. l h h h l?h ? during the data portion of a write sequence, only the lower byte (d [8:0] ) is written into the device. d [35:9] remains unaltered. l h h h ? l?h during the data portion of a write sequence, only the lower byte (d [8:0] ) is written into the device. d [35:9] remains unaltered. h l h h l?h ? during the data portion of a write sequence, only the byte (d [17:9] ) is written into the device. d [8:0] and d [35:18] remains unaltered. h l h h ? l?h during the data portion of a write sequence, only the byte (d [17:9] ) is written into the device. d [8:0] and d [35:18] remains unaltered. h h l h l?h ? during the data portion of a write sequence, only the byte (d [26:18] ) is written into the device. d [17:0] and d [35:27] remains unaltered. h h l h ? l?h during the data portion of a write sequence, only the byte (d [26:18] ) is written into the device. d [17:0] and d [35:27] remains unaltered. h h h l l?h ? during the data portion of a write sequence, only the byte (d [35:27] ) is written into the device. d [26:0] remains unaltered. h h h l ? l?h during the data portion of a write sequence, only the byte (d [35:27] ) is written into the device. d [26:0] remains unaltered. hhhhl?h?no data is written into the device during this portion of a write operation. hhhh?l?hno data is written into the device during this portion of a write operation. [+] feedback [+] feedback
cy7c1161v18, cy7c1176v18 cy7c1163v18, cy7c1165v18 document number: 001-06582 rev. *d page 13 of 29 ieee 1149.1 serial boundary scan (jtag) these srams incorporate a serial boundary scan test access port (tap) in the fbga package. this part is fully compliant with ieee standard 1149.1-2001. the tap operates using jedec standard 1.8v io logic levels. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap co ntroller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are inter- nally pulled up and may be unconne cted. they may alternatively be connected to v dd through a pull up resistor. tdo must be left unconnected. upon power up, the device comes up in a reset state which does not interfere wi th the operation of the device. test access port?test clock the test clock is used only with the tap controller. all inputs are captured on the rising edge of tc k. all outputs are driven from the falling edge of tck. test mode select the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this pin unconnected if the tap is not used. the pin is pulled up internally, resulting in a logic high level. test data in (tdi) the tdi pin is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instruction register, see ?tap controller state diagram? on page 15 tdi is internally pulled up and can be unconnected if the tap is unus ed in an application. tdi is connected to the most signific ant bit (msb) on any register. test data out (tdo) the tdo output pin is used to serially clock data out from the registers. the output is active depending upon the current state of the tap state machine, see ?instruction codes? on page 18 the output changes on the falling edge of tck. tdo is connected to the least significa nt bit (lsb) of any register. performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does no t affect the operation of the sram and may be performed while the sram is operating. at power up, the tap is reset intern ally to ensure that tdo comes up in a high z state. tap registers registers are connected between the tdi and tdo pins and enables data to be scanned into and out of the sram test circuitry. only one register is selected at a time through the instruction registers. data is serially loaded into the tdi pin on the rising edge of tck. data outpu ts on the tdo pin on the falling edge of tck. instruction register three-bit instructions are serial ly loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo pins as shown in ?tap controller block diagram? on page 16. upon power up, the instru ction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in the capture ir state, the two least significant bits are loaded with a binary ?01? pattern to allow fault isolation of the board level serial test path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between tdi and tdo pins. this enables data to be shifted through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all of the input and output pins on the sram. several no connect (nc) pins are also included in the scan register to reserve pins for higher density devices. the boundary scan register is loaded with the contents of the ram input and output ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo pins when the controller is moved to the shift-dr state. the extest, sample/preload and sam ple z instructions can be used to capture the contents of the input and output ring. the ?boundary scan order? on page 19 show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register . the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id regist er has a vendor code and other information described in the ?identification register definitions? on page 18. tap instruction set eight different instructions ar e possible with the three-bit instruction register. all combinations are listed in the ?instruction codes? on page 18. three of these instructions are listed as reserved and must not be used. the other five instructions are described below. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo pins. to execute the instruction once it is shifted in, the tap controller needs to be moved into the update-ir state. [+] feedback [+] feedback
cy7c1161v18, cy7c1176v18 cy7c1163v18, cy7c1165v18 document number: 001-06582 rev. *d page 14 of 29 idcode the idcode instruction causes a vendor-specific 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo pins and enables the idcode to be shifted out of the device when the tap controller enters the shift-dr st ate. the idcode instruction is loaded into the instruction register upon power up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo pins when the tap controller is in a shift-dr state. the sample z command puts the output bus into a high z stat e until the next command is given during the update ir state. sample/preload sample/preload is a 1149.1 mandatory instruction. when the sample/preload instructions are loaded into the instruc- tion register and the tap controller is in the capture-dr state, a snapshot of data on the inputs an d output pins is captured in the boundary scan register. the user must be aware that the tap controller clock only oper- ates at a frequency up to 20 mhz, while the sram clock oper- ates more than an order of magnitude faster. because there is a large difference in the clock frequenc ies, it is possible that during the capture-dr state, an input or output undergoes a transition. the tap then tries to capture a signal while in transition (meta- stable state). this does not harm the device but there is no guar- antee as to the value that is captured. repeatable results are not possible. to guarantee that the boundary sc an register captures the cor- rect value of a signal, the sram signal is stabilized long enough to meet the tap controller's ca pture setup plus hold times (t cs and t ch ). the sram clock input is not captured correctly if there is no way in a design to stop (or slow) the clock during a sam- ple/preload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. preload enables an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation. the shifting of data for the sample and preload phases can occur concurrently when require d?that is, while data captured is shifted out, the preloaded data is shifted in. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift- dr state, the bypass register is placed between the tdi and tdo pins. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. extest the extest instruction enables the preloaded data to be driven out through the system ou tput pins. this inst ruction also selects the boundary scan register to be connected for serial access between the tdi and tdo in the shift-dr controller state. extest output bus tri-state ieee standard 1149.1 ma ndates that the tap controller puts the output bus into a tri-state mode. the boundary scan register has a special bit located at bit 47. when this scan cell, called the ?extest output bus tri-state?, is latched into the preload register during the update-dr state in the tap controller, it directly controls the state of the output (q-bus) pins, when the extest is entered as the current instruction. when high, it enables the output buffers to drive the output bus. when low, this bit places the output bus into a high z condition. this bit is set by entering the sample/preload or extest command, and then shifting the desir ed bit into that cell, during the shift-dr state. during updat e-dr, the value loaded into that shift register cell latches into the preload register. when the extest instruction is entered, this bit directly controls the output q-bus pins. note that this bit is preset high to enable the output when the device is powered up, and also when the tap controller is in the test logic reset state. reserved these instructions are not im plemented but are reserved for future use. do not use these instructions. [+] feedback [+] feedback
cy7c1161v18, cy7c1176v18 cy7c1163v18, cy7c1165v18 document number: 001-06582 rev. *d page 15 of 29 tap controller state diagram figure 2. tap controller state diagram [12] test-logic reset test-logic/ idle select dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0 note 12. the 0/1 next to each state represents the value at tms at the rising edge of tck. [+] feedback [+] feedback
cy7c1161v18, cy7c1176v18 cy7c1163v18, cy7c1165v18 document number: 001-06582 rev. *d page 16 of 29 tap controller block diagram figure 3. tap controller block diagram tap electrical characteristics the tap electrical characteristics table over the operating range follows. [13, 14, 15] parameter description test conditions min max unit v oh1 output high voltage i oh = ? 2.0 ma 1.4 v v oh2 output high voltage i oh = ? 100 a1.6 v v ol1 output low voltage i ol = 2.0 ma 0.4 v v ol2 output low voltage i ol = 100 a0.2v v ih input high voltage 0.65 v dd v dd + 0.3 v v il input low voltage ?0.3 0.35 v dd v i x input and output load current gnd v i v dd ?5 5 a 0 0 1 2 . . 29 30 31 boundary scan register identification register 0 1 2 . . . . 106 0 1 2 instruction register bypass register selection circuitry selection circuitry tap controller tdi tdo tck tms notes 13. these characteristic pertain to the tap inputs (tms, tck, td i and tdo). parallel load levels are specified in the electrical characteristics table. 14. overshoot: v ih (ac) < v ddq + 0.35v (pulse width less than t cyc /2), undershoot: v il (ac) > ? 0.3v (pulse width less than t cyc /2) 15. all voltage referenced to ground. [+] feedback [+] feedback
cy7c1161v18, cy7c1176v18 cy7c1163v18, cy7c1165v18 document number: 001-06582 rev. *d page 17 of 29 tap ac switchi ng characteristics the tap ac switching characteristi cs over the operating range follows. [16, 17] parameter description min max unit t tcyc tck clock cycle time 50 ns t tf tck clock frequency 20 mhz t th tck clock high 20 ns t tl tck clock low 20 ns setup times t tmss tms setup to tck clock rise 5 ns t tdis tdi setup to tck clock rise 5 ns t cs capture setup to tck rise 5 ns hold times t tmsh tms hold after tck clock rise 5 ns t tdih tdi hold after clock rise 5 ns t ch capture hold after clock rise 5 ns output times t tdov tck clock low to tdo valid 10 ns t tdox tck clock low to tdo invalid 0 ns tap timing and test conditions the tap timing and test conditions for the cy7c1161v 18, cy7c1176v18, cy7c1163v18, and cy7c1165v18 follows. [17] t tl t th (a) tdo c l = 20 pf z 0 = 50 gnd 0.9v 50 1.8v 0v all input pulses 0.9v test clock test mode select tck tms test data in tdi test data out t tcyc t tmsh t tmss t tdis t tdih t tdov t tdox tdo notes 16. t cs and t ch refer to the setup and hold time requirements of latching data from the boundary scan register. 17. test conditions are specified using the load in tap ac test conditions. t r /t f = 1 ns. [+] feedback [+] feedback
cy7c1161v18, cy7c1176v18 cy7c1163v18, cy7c1165v18 document number: 001-06582 rev. *d page 18 of 29 identification regi ster definitions instruction field value description cy7c1161v18 cy7c1176v18 cy7c1163v18 cy7c1165v18 revision number (31:29) 000 000 000 000 version number. cypress device id (28:12) 11010010001000101 11010010001001101 11010010001010101 11010010001100101 defines the type of sram. cypress jedec id (11:1) 00000110100 00000110100 00000110100 00000110100 enables unique identification of sram vendor. id register presence (0) 1 1 1 1 indicates the presence of an id register. scan register sizes register name bit size instruction 3 bypass 1 id 32 boundary scan 107 instruction codes instruction code description extest 000 captures the input and output ring contents. idcode 001 loads the id register with the vendor id code and pl aces the register between tdi and tdo. this operation does not affect sram operation. sample z 010 captures the input and output conten ts. places the boundary scan register between tdi and tdo. this forces all sram output drivers to a high z state. reserved 011 do not use: this instruct ion is reserved for future use. sample/preload 100 captures the in put and output ring contents. pl aces the boundary scan register between tdi and tdo. this operation d oes not affect the sram operation. reserved 101 do not use: this instruct ion is reserved for future use. reserved 110 do not use: this instruct ion is reserved for future use. bypass 111 places the bypass register between td i and tdo. this operation does not affect sram operation. [+] feedback [+] feedback
cy7c1161v18, cy7c1176v18 cy7c1163v18, cy7c1165v18 document number: 001-06582 rev. *d page 19 of 29 boundary scan order bit # bump id bit # bump id bit # bump id bit # bump id 0 6r 27 11h 54 7b 81 3g 1 6p 28 10g 55 6b 82 2g 26n 299g 566a 831j 3 7p 30 11f 57 5b 84 2j 4 7n 31 11g 58 5a 85 3k 57r 329f 594a 863j 6 8r 33 10f 60 5c 87 2k 7 8p 34 11e 61 4b 88 1k 8 9r 35 10e 62 3a 89 2l 9 11p 36 10d 63 1h 90 3l 10 10p 37 9e 64 1a 91 1m 11 10n 38 10c 65 2b 92 1l 12 9p 39 11d 66 3b 93 3n 13 10m 40 9c 67 1c 94 3m 1411n 419d 681b 951n 15 9m 42 11b 69 3d 96 2m 16 9n 43 11c 70 3c 97 3p 1711l 449b 711d 982n 18 11m 45 10b 72 2c 99 2p 19 9l 46 11a 73 3e 100 1p 20 10l 47 internal 74 2d 101 3r 2111k 489a 752e 1024r 22 10k 49 8b 76 1e 103 4p 23 9j 50 7c 77 2f 104 5p 24 9k 51 6c 78 3f 105 5n 25 10j 52 8a 79 1g 106 5r 26 11j 53 7a 80 1f [+] feedback [+] feedback
cy7c1161v18, cy7c1176v18 cy7c1163v18, cy7c1165v18 document number: 001-06582 rev. *d page 20 of 29 power up sequence in qdr-ii+ sra during power up, when the doff is tied high, the dll gets locked after 2048 cycles of stab le clock. qdr-ii+ srams must be powered up and initialized in a predefined manner to prevent undefined operations. power up sequence apply power with doff tied high (all other inputs can be high or low) ? apply v dd before v ddq ? apply v ddq before v ref or at the same time as v ref provide stable power and clock (k, k ) for 2048 cycles to lock the dll dll constraints dll uses k clock as its synchronizing input. the input must have low phase jitter, which is specified as t kc var the dll functions at frequencies down to 120 mhz if the input clock is unstable and the dll is enabled, then the dll locks onto an incorrect frequency, causing unstable sram behavior. to avoid this, prov ide 2048 cycles stable clock to relock to the desired clock frequency power up waveforms figure 4. power up waveforms k k fix high (tie to v ddq ) v dd /v ddq doff clock start (clock starts after v dd /v ddq is stable) unstable clock > 2048 stable clock start normal operation ~ ~ ~ ~ v dd /v ddq stable (< + 0.1v dc per 50 ns) [+] feedback [+] feedback
cy7c1161v18, cy7c1176v18 cy7c1163v18, cy7c1165v18 document number: 001-06582 rev. *d page 21 of 29 maximum ratings exceeding maximum ratings may impair the useful life of the device. user guidelines are not tested. storage temperature ............. .............. ..... ?65c to + 150c ambient temperature with powe r applied. ?55c to + 125c supply voltage on v dd relative to gnd .......?0.5v to + 2.9v supply voltage on v ddq relative to gnd ..... ?0.5v to + v dd dc applied to outputs in high z ........ ?0.5v to v ddq + 0.3v dc input voltage [14] ............................... ?0.5v to v dd + 0.3v current into outputs (low)..... .................................... 20 ma static discharge voltage (mil -std-883, m. 3015).. > 2001v latch up current.................................................... > 200 ma operating range range ambient temperature (t a ) v dd [18] v ddq [18] commercial 0c to +70c 1.8 0.1v 1.4v to v dd industrial ?40c to +85c electrical characteristics the dc electrical characteristics over the operating range follows. [15] parameter description test conditions min typ max unit v dd power supply voltage 1.7 1.8 1.9 v v ddq io supply voltage 1.4 1.5 v dd v v oh output high voltage note 19 v ddq /2 ? 0.12 v ddq /2 + 0.12 v v ol output low voltage note 20 v ddq /2 ? 0.12 v ddq /2 + 0.12 v v oh(low) output high voltage i oh = ? 0.1 ma, nominal impedance v ddq ? 0.2 v ddq v v ol(low) output low voltage i ol = 0.1 ma, nominal impedance v ss 0.2 v v ih input high voltage v ref + 0.1 v ddq + 0.15 v v il input low voltage ?0.15 v ref ? 0.1 v i x input leakage current gnd v i v ddq ? 22 a i oz output leakage current gnd v i v ddq, output disabled ? 22 a v ref input reference voltage [21] typical value = 0.75v 0.68 0.75 0.95 v i dd [22] v dd operating supply v dd = max, i out = 0 ma, f = f max = 1/t cyc 300 mhz 850 ma 333 mhz 920 ma 375 mhz 1020 ma 400 mhz 1080 ma i sb1 automatic power down current max v dd , both ports deselected, v in v ih or v in v il f = f max = 1/t cyc , inputs static 300 mhz 250 ma 333 mhz 260 ma 375 mhz 290 ma 400 mhz 300 ma ac electrical characteristics over the operating range follows. [21] parameter description test conditions min typ max unit v ih input high voltage v ref + 0.2 ? v ddq + 0.24 v v il input low voltage ?0.24 ? v ref ? 0.2 v notes 18. power up: is based upon a linear ramp from 0v to v dd (min) within 200 ms. during this time v ih < v dd and v ddq < v dd . 19. output are impedance controlled. i oh = ? (v ddq /2)/(rq/5) for values of 175 < rq < 350 . 20. output are impedance controlled. i ol = (v ddq /2)/(rq/5) for values of 175 < rq < 350 . 21. v ref (min) = 0.68v or 0.46v ddq , whichever is larger, v ref (max) = 0.95v or 0.54v ddq , whichever is smaller. 22. the operation current is calculated with 50% read cycle and 50% write cycle. [+] feedback [+] feedback
cy7c1161v18, cy7c1176v18 cy7c1163v18, cy7c1165v18 document number: 001-06582 rev. *d page 22 of 29 capacitance tested initially and after any design or proc ess change that may affect these parameters. parameter description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v dd = 1.8v v ddq = 1.5v 5pf c clk clock input capacitance 6 pf c o output capacitance 7pf thermal resistance tested initially and after any design or proc ess change that may affect these parameters. parameter description test conditions 165 fbga package unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuri ng thermal impedance, in accordance with eia/jesd51. 17.2 c/w jc thermal resistance (junction to case) 4.15 c/w ac test loads and waveforms figure 5. ac test loads and waveforms 1.25v 0.25v r = 50 5pf including jig and scope all input pulses device r l = 50 z 0 = 50 v ref = 0.75v v ref = 0.75v [23] 0.75v under te s t 0.75v device under te s t output 0.75v v ref v ref output zq zq (a) slew rate = 2 v/ns rq = 250 (b) rq = 250 23. unless otherwise noted, test conditions are based upon signal tr ansition time of 2v/ns, timing reference levels of 0.75v, vr ef = 0.75v, rq = 250 , v ddq = 1.5v, input pulse levels of 0.25v to 1.25v, and output loading of the specified i ol /i oh and load capacitance shown in (a) of ac test loads. [+] feedback [+] feedback
cy7c1161v18, cy7c1176v18 cy7c1163v18, cy7c1165v18 document number: 001-06582 rev. *d page 23 of 29 switching characteristics over the operating range [23, 24] cypress parameter consortium parameter description 400 mhz 375 mhz 333 mhz 300 mhz unit min max min max min max min max t power v dd (typical) to the first access [25] 1?1?1?1?ms t cyc t khkh k clock cycle time 2.50 8.40 2.66 8.40 3.0 8.40 3.3 8.40 ns t kh t khkl input clock (k/k ) high 0.4?0.4?0.4?0.4?t cyc t kl t klkh input clock (k/k ) low 0.4?0.4?0.4?0.4?t cyc t khk h t khk h k clock rise to k clock rise (rising edge to rising edge) 1.06?1.13?1.28?1.40? ns setup times t sa t avkh address setup to k clock rise 0.4 ? 0.4 ? 0.4 ? 0.4 ? ns t sc t ivkh control setup to k clock rise (rps , wps ) 0.4?0.4?0.4?0.4? ns t scddr t ivkh double data rate control setup to clock (k, k ) rise (bws 0 , bws 1, bws 2 , bws 3 ) 0.28?0.28?0.28?0.28? ns t sd t dvkh d [x:0] setup to clock (k/k ) rise 0.28?0.28?0.28?0.28? ns hold times t ha t khax address hold after k clock rise 0.4 ? 0.4 ? 0.4 ? 0.4 ? ns t hc t khix control hold after k clock rise (rps , wps ) 0.4?0.4?0.4?0.4? ns t hcddr t khix double data rate control hold after clock (k/k ) rise (bws 0 , bws 1, bws 2 , bws 3 ) 0.28?0.28?0.28?0.28? ns t hd t khdx d [x:0] hold after clock (k/k ) rise 0.28?0.28?0.28?0.28? ns output times t co t chqv k/k clock rise to data valid ? 0.45 ? 0.45 ? 0.45 ? 0.45 ns t doh t chqx data output hold after output k/k clock rise (active to active) ?0.45 ? ?0.45 ? ?0.45 ? ?0.45 ? ns t ccqo t chcqv k/k clock rise to echo clock valid ? 0.45 ? 0.45 ? 0.45 ? 0.45 ns t cqoh t chcqx echo clock hold after k/k clock rise ?0.45 ? ?0.45 ? ?0.45 ? ?0.45 ? ns t cqd t cqhqv echo clock high to data valid ? 0.2 0.2 0.2 0.2 ns t cqdoh t cqhqx echo clock high to data invalid ?0.2 ? ?0.2 ? ?0.2 ? ?0.2 ? ns t cqh t cqhcql output clock (cq/cq ) high [26] 0.81?0.88?1.03?1.15? ns t cqhcq h t cqhcq h cq clock rise to cq clock rise [26] (rising edge to rising edge) 0.81?0.88?1.03?1.15? ns t chz t chqz clock (k/k ) rise to high z (active to high z) [27, 28] ?0.45?0.45?0.45?0.45ns t clz t chqx1 clock (k/k ) rise to low z [27, 28] ?0.45 ? ?0.45 ? ?0.45 ? ?0.45 ? ns t qvld t qvld echo clock high to qvld valid [29] ?0.20 0.20 ?0.20 0.20 ? 0.20 0.20 ?0.20 0.20 ns notes 24. when a part with a maximum frequency above 300 mhz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being operated and outputs data with the output timings of that frequency range. 25. this part has a voltage regulator internally; t power is the time that the power needs to be supplied above v dd minimum initially before a read or write operation can be initiated. 26. these parameters are extrapolated from the input timing parameters (t khk h ? 250 ps, where 250 ps is the internal jitter. an input jitter of 200 ps (t kc var ) is already included in the t khk h ). these parameters are only guaranteed by design and are not tested in production. 27. t chz , t clz are specified with a load capacitance of 5 pf as in part (b) of ac test loads and waveforms . transition is measured 100 mv from steady state voltage. 28. at any voltage and temperature t chz is less than t clz and t chz less than t co . 29. t qvld spec is applicable for both risi ng and falling edges of qvld signal. [+] feedback [+] feedback
cy7c1161v18, cy7c1176v18 cy7c1163v18, cy7c1165v18 document number: 001-06582 rev. *d page 24 of 29 dll timing t kc var t kc var clock phase jitter ? 0.20 ? 0.20 ? 0.20 ? 0.20 ns t kc lock t kc lock dll lock time (k) 2048 ? 2048 ? 2048 ? 2048 ? cycles t kc reset t kc reset k static to dll reset [30] 30?30?30?30? ns switching characteristics over the operating range [23, 24] (continued) cypress parameter consortium parameter description 400 mhz 375 mhz 333 mhz 300 mhz unit min max min max min max min max note 30. hold to >v ih or cy7c1161v18, cy7c1176v18 cy7c1163v18, cy7c1165v18 document number: 001-06582 rev. *d page 25 of 29 switching waveforms read/write/deselect sequence figure 6. waveform for 2.5 cycle read latency [31, 32, 33] t kh t kl t cyc t khkh t t t t sa ha sc hc t hd t sc t hc a0 a1 a2 a3 t t sd hd t sd d11 d10 d12 d13 d30 d31 d32 d33 d a wps rps k k t nop read nop write read write 1 23 4 567 8 cq cq q t cqoh ccqo t clz t t co t doh t cqdoh cqd t t ch z t cqoh ccqo t t qvld qvld qvld dont care undefined (read latency = 2.5 cycles) q00 q01 q20 q02 q21 q03 q22 q23 t cqh t cqhcqh notes 31. q00 refers to output from address a0. q01 refers to output from the next internal burst address following a0, i.e., a0+1. 32. outputs are disabled (high z) one clock cycle after a nop. 33. in this example, if address a2 = a1, then data q20 = d10 and q21 = d11. write data is forwarded immediately as read results. this note applies to the whole diagram. [+] feedback [+] feedback
cy7c1161v18, cy7c1176v18 cy7c1163v18, cy7c1165v18 document number: 001-06582 rev. *d page 26 of 29 ordering information not all of the speed, package and temperature ranges are avai lable. contact your local sales representative or visit www.cypress.com for actual products offered. speed (mhz) ordering code package diagram package type operating range 400 cy7c1161v18-400bzc 51-85180 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) commercial cy7c1176v18-400bzc CY7C1163V18-400BZC cy7c1165v18-400bzc cy7c1161v18-400bzxc 51-85180 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) pb-free cy7c1176v18-400bzxc cy7c1163v18-400bzxc cy7c1165v18-400bzxc cy7c1161v18-400bzi 51-85180 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) industrial cy7c1176v18-400bzi cy7c1163v18-400bzi cy7c1165v18-400bzi cy7c1161v18-400bzxi 51-85180 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) pb-free cy7c1176v18-400bzxi cy7c1163v18-400bzxi cy7c1165v18-400bzxi 375 cy7c1161v18-375bzc 51-85180 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) commercial cy7c1176v18-375bzc cy7c1163v18-375bzc cy7c1165v18-375bzc cy7c1161v18-375bzxc 51-85180 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) pb-free cy7c1176v18-375bzxc cy7c1163v18-375bzxc cy7c1165v18-375bzxc cy7c1161v18-375bzi 51-85180 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) industrial cy7c1176v18-375bzi cy7c1163v18-375bzi cy7c1165v18-375bzi cy7c1161v18-375bzxi 51-85180 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) pb-free cy7c1176v18-375bzxi cy7c1163v18-375bzxi cy7c1165v18-375bzxi [+] feedback [+] feedback
cy7c1161v18, cy7c1176v18 cy7c1163v18, cy7c1165v18 document number: 001-06582 rev. *d page 27 of 29 333 cy7c1161v18-333bzc 51-85180 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) commercial cy7c1176v18-333bzc cy7c1163v18-333bzc cy7c1165v18-333bzc cy7c1161v18-333bzxc 51-85180 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) pb-free cy7c1176v18-333bzxc cy7c1163v18-333bzxc cy7c1165v18-333bzxc cy7c1161v18-333bzi 51-85180 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) industrial cy7c1176v18-333bzi cy7c1163v18-333bzi cy7c1165v18-333bzi cy7c1161v18-333bzxi 51-85180 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) pb-free cy7c1176v18-333bzxi cy7c1163v18-333bzxi cy7c1165v18-333bzxi 300 cy7c1161v18-300bzc 51-85180 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) commercial cy7c1176v18-300bzc cy7c1163v18-300bzc cy7c1165v18-300bzc cy7c1161v18-300bzxc 51-85180 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) pb-free cy7c1176v18-300bzxc cy7c1163v18-300bzxc cy7c1165v18-300bzxc cy7c1161v18-300bzi 51-85180 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) industrial cy7c1176v18-300bzi cy7c1163v18-300bzi cy7c1165v18-300bzi cy7c1161v18-300bzxi 51-85180 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) pb-free cy7c1176v18-300bzxi cy7c1163v18-300bzxi cy7c1165v18-300bzxi ordering information (continued) not all of the speed, package and temperature ranges are avai lable. contact your local sales representative or visit www.cypress.com for actual products offered. speed (mhz) ordering code package diagram package type operating range [+] feedback [+] feedback
cy7c1161v18, cy7c1176v18 cy7c1163v18, cy7c1165v18 document number: 001-06582 rev. *d page 28 of 29 package diagram figure 7. 165-ball fbga (13 x 15 x 1.4 mm), 51-85180 a 1 pin 1 corner 15.000.10 13.000.10 7.00 1.00 ?0.50 (165x) ?0.25 m c a b ?0.05 m c b a 0.15(4x) 0.350.06 seating plane 0.530.05 0.25 c 0.15 c pin 1 corner top view bottom view 2 3 4 5 6 7 8 9 10 10.00 14.00 b c d e f g h j k l m n 11 11 10 9 8 67 5 4 3 2 1 p r p r k m n l j h g f e d c b a a 15.000.10 13.000.10 b c 1.00 5.00 0.36 - 0.06 +0.14 1.40 max. solder pad type : non-solder mask defined (nsmd) notes : package weight : 0.475g jedec reference : mo-216 / design 4.6c package code : bb0ac 51-85180-*a [+] feedback [+] feedback
document number: 001-06582 rev. *d revised march 06, 2008 page 29 of 29 qdr? is a trademark of cypress semiconductor corp. qdr rams and quad data rate rams comprise a new family of products developed by cypress, idt, nec, renesas, and samsung. all product and company names mentioned in this document are the trademarks of their respective holders. cy7c1161v18, cy7c1176v18 cy7c1163v18, cy7c1165v18 ? cypress semiconductor corporation, 2006-2008. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page document title: cy7c1161v18/cy7c1176v18/cy7c1163v18/cy7 c1165v18, 18-mbit qdr?-ii+ sram 4-word burst archi- tecture (2.5 cycle read latency) document number: 001-06582 rev. ecn no. issue date orig. of change description of change ** 430351 see ecn nxr new data sheet *a 461654 see ecn nxr revised the mpns from cy7c1176bv18 to cy7c1176v18 cy7c1163bv18 to cy7c1163v18 cy7c1165bv18 to cy7c1165v18 changed t th and t tl from 40 ns to 20 ns, changed t tmss , t tdis , t cs , t tmsh , t tdih , t ch from 10 ns to 5 ns and changed t tdov from 20 ns to 10 ns in tap ac switching characteristics table modified power up waveform *b 497629 see ecn nxr changed the v ddq operating voltage to 1.4v to v dd in the features section, in operating range table and in the dc electrical characteristics table added foot note in page 1 changed the maximum rating of ambient temperature with power applied from ?10c to +85c to ?55c to +125c changed v ref (max) spec from 0.85v to 0.95v in the dc electrical character- istics table and in the note below the table updated foot note 22 to specify overshoot and undershoot spec updated ja and jc values removed x9 part and its related information updated footnote 25 *c 1167806 see ecn vkn/kkvtmp converted from preliminary to final added x8 and x9 parts changed i dd values from 800 ma to 1080 ma for 400 mhz, 766 ma to 1020 ma for 375 mhz, 708 ma to 920 ma for 333 mhz, 663 ma to 850 ma for 300 mhz changed i sb values from 235 ma to 300 ma for 400 mhz, 227 ma to 290 ma for 375 mhz, 212 ma to 260 ma for 333 mhz, 201 ma to 250 ma for 300 mhz changed t cyc(max) spec to 8.4 ns for all speed bins changed ja value from 13.48 c/w to 17.2 c/w updated ordering information table *d 2199066 see ecn vkn/ aesa added footnote# 22 related to i dd [+] feedback [+] feedback

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